The invention relates to SCR-type ESD protection structures. More particularly, it relates to SCR-type ESD protection structures suitable for implementation using SOI or triple well processes.
Analog circuits typically display sensitivity to excessive voltage levels. Transients, such as electrostatic discharges (ESD) can cause the voltage handling capabilities of the analog circuit to be exceeded, resulting in damage to the analog circuit. Clamps have been devised to shunt current to ground during excessive voltage peaks.
Different clamps have been developed, each with different characteristics, such as the grounded gate NMOS device (GGNMOS). However, GGNMOS devices are not only large, consuming a lot of space on a chip, they also suffer from the disadvantage that they support only limited current densities. The protection capability of an ESD protection device can be defined as the required contact width of the structure required to protect against an ESD pulse amplitude, or, stated another way, as the maximum protected ESD pulse amplitude for a given contact width. Thus, the smaller the contact width for a given ESD pulse amplitude protection, the better.
Furthermore process considerations are important when deciding on the type of ESD device to implement. It is clearly desirable to make use of existing process steps as much as possible and avoid having to introduce new process steps. One type of ESD protection solution that is highly efficient and is commonly used in BiCMOS, BCD, SOI, and triple well CMOS technology, is the silicon-controlled rectifier (SCR). In fact, in the case of SOI and triple well process, SCRs currently provide the only ESD solution due to severe process design rule limitations in these two processes.
As discussed below, SCRs are essentially lateral structures in which carriers cross laterally over substantially vertically extending junctions. Another defining characteristic of SCRs which make them highly desirable as ESD protection devices is their double injection characteristic which provides for high current densities.
A silicon-controlled rectifier (SCR), such as the one illustrated in FIG. 1, can be seen as a device that provides an open circuit between a first node and a second node when the voltage across the first and second nodes is positive and less than a trigger voltage. When the voltage across the first and second nodes rises to be equal to or greater than the trigger voltage, the SCR provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the SCR maintains the current path as long as the voltage across the first and second nodes is equal to or greater than a holding voltage that is lower than the trigger voltage. As a result of these characteristics, SCRs have been used to provide ESD protection. When used for ESD protection, the first node becomes a to-be-protected node, and the second node is typically connected to ground. The SCR operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected node, and a minimum voltage (also known as a latch-up voltage) defined by any dc bias on the to-be-protected node.
Thus, when the voltage across the to-be-protected node and the second node is less than the trigger voltage, the SCR provides an open circuit between the to-be-protected node and the second node. However, when the to-be-protected node receives a voltage spike that equals or exceeds the trigger voltage, such as when an ungrounded human-body discharge occurs, the SCR provides a low-resistance current path from the to-be-protected node to the second node. In addition, once the ESD event has passed and the voltage on the to-be-protected node falls below the holding voltage, the SCR again provides an open circuit between the to-be-protected node and the second node.
FIG. 1 shows a cross-sectional view that illustrates a conventional SCR 100. As shown in FIG. 1, SCR 100 has a n-well 112 which is formed in a p-type semiconductor material 110, such as a substrate or a well, and a n+ region 114 and a p+ region 116 which are formed in n-well 112. The n+ and p+ regions 114 and 116 are both connected to a to-be-protected node 120. As further shown in FIG. 1, SCR 100 also has a n+ region 122 and a p+ region 124 formed in semiconductor material 110. The n+ and p+ regions 122 and 124 are both connected to an output node 126.
In operation, when the voltage across nodes 120 and 126 is positive and less than the trigger voltage, the voltage reverse biases the junction between n-well 112 and p-type material 110. The reverse-biased junction, in turn, blocks charge carriers from flowing from node 120 to node 126. However, when the voltage across nodes 120 and 126 is positive and equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication.
The breakdown of the junction causes a large number of holes to be injected into material 110, and a large number of electrons to be injected into n-well 112. The increased number of holes increases the potential of material 110 in the region that lies adjacent to n+ region 122, and eventually forward biases the junction between material 110 and n+ region 122.
When the increased potential forward biases the junction, a npn transistor that utilizes n+ region 122 as the emitter, p-type material 110 as the base, and n-well 112 as the collector turns on. When turned on, n+ (emitter) region 122 injects electrons into (base) material 110. Most of the injected electrons diffuse through (base) material 110 and are swept from (base) material 110 into (collector) n-well 112 by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well 112 are then collected by n+ region 114.
A small number of the electrons injected into (base) material 110 recombine with holes in (base) material 110 and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material 110 by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor, thereby providing the base current.
The electrons that are injected and swept into n-well 112 also decrease the potential of n-well 112 in the region that lies adjacent to p+ region 116, and eventually forward bias the junction between p+ region 116 and n-well 112. When the decreased potential forward biases the junction between p+ region 116 and n-well 112, a pnp transistor formed from p+ region 116, n-well 112, and material 110, turns on.
When turned on, p+ emitter 116 injects holes into base 112. Most of the injected holes diffuse through (base) n-well 112 and are swept from (base) n-well 112 into (collector) material 110 by the electric field that extends across the reverse-biased junction. The holes in (collector) material 110 are then collected by p+ region 124.
A small number of the holes injected into (base) n-well 112 recombine with electrons in (base) n-well 112 and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n-well 112 as a result of the broken-down reverse-biased junction, and n-well 112 being the collector of the npn transistor. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, as noted above, the holes swept into (collector) material 110 also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region 122. Thus, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region 122 injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region 116 injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
Thus, as mentioned above, one of the advantages of SCR 100 over other ESD protection devices, such as a grounded-gate MOS transistor, is the double injection provided by n+ region 122 and p+ region 116 of SCR 100. With double injection, SCR 100 provides current densities (after snapback) that are about ten times greater than the densities provided by a grounded-gate MOS device.
However, it is desirable to, increase the robustness of ESD protection devices such as SCRs. Also, conventional SCRs fail to address dual polarity voltage swings.
The present invention provides a SCR-like structure that is very robust, has a low triggering voltage, is implementable in complementary structures to accommodate both positive and negative voltage swings, and is small relative to a conventional SCR.
The invention provides a standalone ESD protection structure that includes a BJT structure in which the collector sinker and buried layer are replaced with a sinker and buried layer of the opposite polarity. The structure may include a SCR-like emitter region, and the opposite polarity sinker and buried layer may extend from the SCR-like emitter region. The BJT structure may be a NPN or a PNP structure extending substantially vertically. The collector contact of the BJT structure may be eliminated to provide for a smaller protection structure.
Further, according to the invention, there is provided, an ESD protection structure comprising a BJT-like structure with a buried layer, wherein the polarity of the buried layer is reversed. Typically the opposite polarity buried layer is contacted through a sinker of said opposite polarity to define an emitter of a SCR-like structure. The buried layer may be a n-buried layer or p-buried layer. The collector contact of the device may be eliminated to provide a two-contact device. Typically the BJT emitter and base are connected to a first contact, and the emitter of the SCR-like structure is connected to a second contact. The first contact may define an anode contact and the second contact a cathode contact or vice versa.
Still further, according to the invention, there is provided, an ESD protection structure for protecting against negative voltage swings, implementable using SOI (Silicon on insulator) or triple well process steps, comprising a PNP BJT-like structure with a n-buried layer. Typically the n-buried layer is contacted through a n-sinker to define an emitter of a SCR-like structure. The collector of the BJT-like structure may be eliminated.
Still further, according to the invention, there is provided SCR-like triggering structure-that includes a substantially vertically configured BJT structure, a SCR emitter, and a buried layer in contact with the SCR emitter, and which is of opposite polarity to the collector of the BJT structure.